Functional Verification

FirstPass engineers are verification experts. As ASIC/FPGA and system capabilities have exponentially increased, verification methodologies have changed dramatically. The randomized, object oriented approach to verification has greatly increased the efficiency and quality of pre-silicon simulation. Verification metrics such as code coverage and functional coverage allow us to answer the question “When are we done?” These metrics also provide a good understanding of risk and program tracking. Widespread use of assertions in RTL coding have reduced debug time and increased correlation between specification, design and verification. Formal verification is showing tremendous capabilities as well. We are experts with System Verilog, Vera, and Specman as well as VHDL and Verilog testbenches for lower complexity devices. This verification methodology is the key to FirstPass success!


  • Verification Plan to specify DV approach and function
  • Verification Requirements Matrix to define and track Verification Requirements, coverage methods, priorities
  • Automated reporting of actual coverage results versus Verification Requirements
  • Reviews to monitor and track coverage closure


  • Constrained-random generation of stimulus
  • Coverage-driven Verification
  • Stand-alone intelligent agents, checkers, scoreboards
  • Assertions in RTL and Verification code


  • SystemVerilog and UVM/OVM/AVM/VMM
  • Fewer test cases, more randomization of setup/traffic
  • Verification IP integration
  • Automated reporting of actual coverage results versus verification requirements
  • Directed testing where necessary or more efficient
  • Verilog, VHDL, e, C/C++/SystemC models and testbenches


  • Mentor ModelSim, Questa
  • Cadence Incisive
  • Synopsys VCS
  • Aldec Riviera-PRO