Physical Design

FirstPass engineers have successfully performed physical implementation of designs onto FPGAs, Gate Arrays, Standard Cell, and transistor level full custom ASICs. We have designed libraries along with Design Rule Check files and Electrical Rule Check files. We have taken many designs from RTL to GDSII release to foundry, and performed all physical verification checks including timing, power, logic equivalency, layout versus schematic, on chip variation, cross talk, etc. Tight integration with the design functions results in a manageable, high performance, low risk and efficient physical implementation.

  • Full custom layout
    • Device matching
    • Parasitic extraction
    • LOD effects
    • Well proximity effects
  • LEF and .LIB generation
  • Place and route
    • Full chip floorplanning
    • Hierarchical and flat design
    • IP integration
    • Physical constraint generation
    • STA and timing closure
    • Power bussing and power analysis
    • Signal integrity
    • Physical verification (LVS, DRC, ERC)