Careers

FirstPass Engineering has been providing digital and analog solutions for their customers since 1993. Whether it be designing in the latest ASIC/FPGA technology or utilizing the most advanced verification methods to assure that a customer’s product is RIGHT THE FIRST TIME, you will find FirstPass Engineering to be an exciting work environment that offers an exceptionally high level of exposure to a wide variety of products with many leading-edge commercial, military, and aerospace companies.

We are looking for design and verification engineers in the Castle Rock and Phoenix offices with varying levels of experience that relish the opportunity to utilize, broaden, and grow their skills and enjoy the continued success and growth that FirstPass Engineering has experienced for over 20 years. Providing highly specialized solutions across large market segments for an endless variety of products is challenging and rewarding, and offers significant opportunity for personal growth as well as leadership opportunities.

Careers

We are always seeking highly qualified Design and Verification Engineers. We offer competitive compensation packages, outstanding benefits, and a high quality-of-life work environment.

For consideration, please send your resume to careers@firstpasseng.com.


Current Job Openings

Unless otherwise noted, openings are available at both Castle Rock, CO and Phoenix, AZ sites

Senior ASIC Verification Engineer

The ideal candidate will have a Bachelor’s Degree in Electrical Engineering, Computer Engineering, or Computer Science with five to ten years of experience in the verification of ASIC/FPGA devices.

The following skills and experience are required:

  • Strong understanding of verification process and flow
    • Join a project at any phase with minimal disruption
    • Participate as a lead and/or contributor
    • Quickly adapt to a variety of different environments, methods and standards
  • Ability to create a high-level verification plan
    • Derivation of verification requirements from design requirements
    • Derivation of project schedule from verification requirements
    • Architecting a complex test environment
    • Identification and integration of re-use
  • Ability to create a complex constrained random test environment
    • Setup, build and run test benches
    • Develop agents for complex interfaces (protocol/retries/split transactions)
    • Application of direct and random methods
    • Application of coverage analysis (types and convergence methods)
    • Analyzing and debugging failures to establish root cause
    • Application of assertions
  • Strong understanding of Object Oriented Programming (classes, methods, polymorphism)
  • Use of a high-level language for verification, such as SystemVerilog C++, Java, etc.
  • Experience with verification methodologies (OVM/UVM)
  • Highly skilled with one or more industry standard simulation tools such as Mentor Questa-ModelSim, Synopsys VCS, or Cadence NCSIM
  • Strong understanding of typical design structures (FIFO’s, pipelines, memories, state machines, etc.)
  • Strong understanding of standard protocols (PCI Express, Ethernet, etc.)
  • Comfortable and confident interacting with customers
  • Excellent written and verbal communication skills


The following additional skills and experiences would be a plus:

  • Experience verifying hierarchically partitioned large ASICs
  • SystemVerilog/C++ co-simulation
  • Overall knowledge of the ASIC development process
  • RTL design experience
  • Ability to train/mentor junior engineers


Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).

CPU Modeling Engineer

The ideal candidate will have a Bachelor’s Degree in Electrical Engineering with five or more years of experience in behavioral modeling and Verilog/C co-simulating microprocessor designs.

Job Description: The candidate will be responsible for integration of C models into Verilog simulation environment for an advanced RISC CPU.  The models will vary in levels of abstraction and will require custom designed API’s that connect them to Verilog over DPI.  Additional co-simulation models will be developed that replace RTL modules with C based behavioral models to support both verification and customer demos of the target application including a multiprocessor framework. Candidate will be responsible for debug and tracing tools which must be designed robustly for simulation as well as correlation to the silicon product. Candidate will work closely with micro-architect, verification and design engineers to ensure the API’s support all design debug and verification requirements in a scalable and maintainable manner.

The following skills and experience are required:

  • Direct experience working with C behavioral models, System Verilog, and DPI to verify microprocessor designs.
  • Strong software design skills in creating C level wrapper for C++, designing new API’s, and working with diverse set of engineering teams to realize complete simulation solutions.
  • Knowledge and experience of computer architecture, multiprocessing, and fundamentals including RISC microarchitecture and pipeline design concepts.
  • Strong software design skills in C, C++, Python, Linux, and Verilog DPI.


The following additional skills and experiences would be a plus:

  • Effective at identifying performance-driven issues and using modeling to assist with convergence on architectural trade-offs
  • Familiarity with System Verilog and UVM verification architecture.


Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).

CPU Verification Engineer

The ideal candidate will have a Bachelor’s Degree in Electrical Engineering, Computer Engineering, or Computer Science with five to ten years of experience in the design/verification of ASIC/IC devices.

Job Description: The candidate will be responsible for definition, implementation, debug, and maintenance of CPU architecture verification test suites utilizing extensive Assembly and C level code and interfacing into a System Verilog simulation environment. This person must interface with designers and micro-architects for ensuring coverage goals are established and realized. Test design will span multiple levels of system hierarchy running on a custom 64-bit RISC supercomputer.

The following skills and experience are required:

  • Direct experience in design or verification of high performance microprocessors along with broad software design skills
  • Proficient in designing CPU hardware specific tests in assembly language and in C
  • Working knowledge of CPU systems architecture and debugging in SystemVerilog based verification environments
  • Proficient with at least one scripting language (Perl/Python)


The following additional skills and experiences would be a plus:

  • Experience establish coverage goals, writing test plans, and organizing verification suites
  • Familiarity with randomized verification techniques
  • Understanding of compilers


Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).

Software Development Engineer

The ideal candidate will have a Bachelor’s Degree in Computer Engineering, Computer Science, or Software Engineering with five to ten years of experience in middleware software development.

Job Description: The candidate will be responsible for definition, implementation, debug, and maintenance of middleware software targeted for a custom 64-bit RISC supercomputer system utilizing extensive Assembly and C level code. This person must interface with product development software teams, CPU verification and behavioral modeling teams and ASIC hardware development teams.

The following skills and experience are required:

  • Designing and debugging high performance multithreaded algorithms in C and Assembly
  • Designing low level code and data structures in C and in-line Assembly code
  • System Programming including:
    • Realtime interrupt driven programming
    • Multi-processor distributed programming
    • Complex Memory Management
  • Using LLVM Tool chain including disassemblers and debuggers
  • Working with and debugging assembly level instruction traces
  • Implementing and maintaining GNU Makefiles
  • Software performance profiling and performance driven code improvements
  • Object oriented C++ design (C++11 or newer)
  • Fluent in Linux scripting and automation
  • Software Verification Methods
  • Proficient in debugging code on hardware simulators and real hardware


The following additional skills and experiences would be a plus:

  • Collaborates with team members do develop abstract concepts into software frameworks and low-level implementation
  • Authors and presents software development and verification plans
  • Strong communication skills


Must be a US Person as defined in EAR 15 CFR Part 772 and ITAR 22 CFR Section 120.15, which includes US Citizenship, US Permanent Residence, or a Protected Person under 8 U.S.C. 1324b(a)(3).